If a so-called system LSI, in which an analog circuit and a digital circuit are combined, contains a plurality of power supply systems, such as an analog power supply and a logic power supply, power-on-sequences are specified in the specifications for such a system LSI.
Following power-on-sequences other than that specified causes a transient surplus current to flow in a circuit.
For example, in a system LSI that drives a circuit operating on an analog power supply with a signal from a circuit operating on a logic power supply, the level of the signal from the circuit operating on the logic power supply becomes indefinite for a period of time between turning on of the analog power supply and turning on of the logic power supply. For this reason, in the circuit operating on the analog power supply, a MOS transistor receiving a signal from the circuit operating on the logic power supply experiences a surplus current flow due to an indefinite gate voltage, resulting in the increased drainage of batteries that drive the above system LSI.
Consequently, focusing on a level shift circuit that receives a logic signal and outputs a signal to an analog circuit, it is conceivable that the level of an output signal from the level shift circuit is prevented from becoming indefinite for a period of time between turning-on of the analog power supply and turning-on of the logic power supply.
For example, Japanese Laid-open patent Publication No. 10-336007 describes a level shift circuit that couples an analog power supply with a node in the level shift circuit by capacitive coupling, thereby fixing, in conjunction with turning on of the analog power supply, the potential at a node which is expected to cause the level shift circuit to be at an indefinite potential. Also, Japanese Laid-open patent Publication No 10-163854 describes a level shift circuit that couples, by capacitive coupling, an analog power supply or a ground power supply with a former-stage node in an output buffer constituting the level shift circuit, thereby fixing the potential at the above-described former-stage node in conjunction with turning on of the analog power supply.
In the above-described level shift circuit, a node potential is fixed by capacitive coupling. Accordingly, it takes time to cause electric charge to be built up in the capacitance until the node potential is fixed after an analog power supply is turned on.
Particularly focusing on an output buffer that constitutes a level shift circuit and drives a load connected to the level shift circuit for a period of time until a node potential in the level shift circuit is fixed, the level of a signal from the output buffer in the level shift circuit becomes indefinite until the potential at a former-stage node in the output buffer becomes fixed.
Consequently, a surplus current flows in the level shift circuit and the analog circuit during a period of time from when a node potential in the level shift circuit is not fixed after an analog power supply is turned on, until a logic power supply is turned on.
In other words, a penetrating current flows in a P-type MOS transistor and an N-type MOS transistor which constitute the output buffer in the level shift circuit, resulting in occurrence of a surplus current flow.
Since the analog circuit that operates with a signal from the above output buffer is subjected to an indefinite level signal, a MOS transistor subjected to such an indefinite signal in the analog circuit experiences a penetrating current flow, resulting in occurrence of a surplus current.